Researchers at the University of Illinois Urbana-Champaign have fabricated working monolithic three‑dimensional (3D) circuits from standard single‑crystalline silicon, a long‑sought goal that could extend Moore’s Law by another generation. The team, led by materials science professor Qing Cao, published their work in Nature. Instead of shrinking transistors further, they stack multiple active layers vertically like replacing a sprawling suburb with high‑rises.
The breakthrough solves two problems that have frustrated earlier attempts at monolithic 3D integration: thermal budget and material quality. Upper layers must be processed below 400 °C to avoid damaging underlying metal interconnects. Previous approaches that relied on novel semiconductors performed poorly, nullifying the benefits of 3D stacking.
Cao’s group starts with ultrathin, freestanding silicon membranes less than 10 nanometres thick, peeled from a donor wafer. Using a simple rolling transfer that operates at only 200 °C, they laminate these membranes onto a substrate that already contains finished circuitry. To stay within the low temperature constraint, the team abandons conventional high‑temperature doping and instead uses heavily pre‑doped “junctionless” transistors. Because the membranes are extremely thin, the gate can still control the channel effectively. The researchers report device yields of 98–100% in lab conditions, a level that hints at industrial viability. They built three stacked layers of 625 transistors each, achieving output current densities comparable to conventional bulk‑silicon devices and at least three to four times higher than monolithic 3D attempts based on alternative materials.
The findings open a plausible path toward denser, more powerful AI accelerators and memory chips without shrinking transistors further. The team’s work was conducted within the Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP), which counts IBM, Intel, and TSMC as industry partners.