Researchers at the Institute of Science Tokyo have developed a new approach to building high-performance computer chips for artificial intelligence (AI) systems. AI needs chips that process large amounts of data quickly. Instead of using single chips, modern designs place several chips close together in one package. The difficulty is keeping the chips accurately positioned, allowing fast communication between them, and removing the heat that builds up when they work at high speed.
The researchers developed three related methods that work together under the name BBCube. The first method is a precise way of placing chips onto a larger silicon base. This placement reduces the gaps between chips to a very small distance. The second method creates electrical pathways that connect the chips without the small metal bumps normally used. These pathways are formed after the chips are already in place. Because the bumps are omitted, more connections can fit into the same space. Calculations suggest this arrangement can increase the total amount of data that moves between chips by a large factor while keeping signal quality similar to older designs.
Advances in heat control and overall design
The third method addresses heat. Dense chip arrangements generate more heat, which can slow performance or damage components. Simulations showed that a special waffle-like wafer structure lowers thermal resistance, meaning heat flows away more easily. In addition, a detailed thermal analysis technique examines heat distribution across an entire chip at very fine resolution, using a large number of calculation points. This makes it possible to predict and manage hot spots in new designs.
Together the three methods form a single platform intended for advanced chip arrangements known as 2.5D and 3D integration. The announcement states that the combination of closer chip placement, denser connections without bumps, and better heat handling can support more powerful yet energy-efficient systems for AI accelerators and high-performance computing. Further development of these techniques may lead to more compact chip architectures in the future.
This research was presented at the 2026 Symposium on VLSI Technology and Circuits.